Ph.D. Dissertation Fast Transient and High Efficiency Voltage-Regulated PWM Buck Converters
Jung-Duk Suh
Department of Electrical and Computer Engineering
The Graduate School
Sungkyunkwan University
2019
Abstract
Fast Transient and High Efficiency Voltage-Regulated
PWM Buck Converters
This dissertation proposes three pulse-width modulation (PWM) buck
converter architectures; two for fast load transient and one for high efficiency.
A fast load transient response for small overshoot or undershoot is very
important to designing switching regulator because dynamic voltage scaling is
regarded as an effective power management solution. The transient response
in the conventional voltage mode converter is limited since a type-3
compensator with large capacitors is used. So, it is important to improve slow
transient response problems. Also, improving the efficiency under the light load
condition of switching regulators is a very important design because of many
portable devices stay in standby mode. In common PWM buck converters, the
switching loss is dominant in the light load. So, to improve the performance of
PWM buck converters in terms of the light-load efficiency, the switching power
consumption should be minimized.
In this dissertation, to overcome the speed limitation of the PWM control and
the light load efficiency, PWM buck converters that can improve both the load
transient response and the light load efficiency are proposed. First, a DC-DC
converter with active ramp tracking control (ARTC) is presented. When the
difference between the output voltage and reference voltage is increased to the
threshold voltage in the load transient situation, the ramp bias voltages change
and generate a full duty signal to the power switches. This helps restore the
output voltage to the reference voltage, improving the load transient response
speed and decreasing the overshoot/undershoot at the output voltage. The
proposed converter with ARTC improves the load transient response speed and
decreases the overshoot/undershoot at the output voltage. This proposed buck
converter with ARTC can reduce the overshoot/undershoot at the output by up
to 61.1% and the recovery time up to 60.0 % for a 450-mA load current step.
Second, a DC-DC converter with inductor current slope control (ICSC) is
presented. In load transient period, the slope of the inductor current is increased
two times by connecting the parallel inductor of same size as main inductor. It
can recover the output voltage quickly and have a consistent fast response time
regardless of the load current step size and output voltage. This proposed buck
converter with ICSC simulated in a 65-nm CMOS technology reduces the
overshoot/undershoot at the output by up to 54.4% and the recovery time up to
82.6% for a 450-mA load current step. Third, a DC-DC converter with chargerecycling
gate-voltage swing control is presented. This proposed converter
with charge-recycling gate-voltage swing control can improve the power
efficiency by reducing the gate-driving loss at the light load. This proposed
converter controls the gate-voltage swing with charge-recycling structure
according to the load current and has the gate-driving loss reduced by up to
87.7% and 47.2% compared to the conventional full-swing and low-swing
designs, respectively. The maximum power conversion efficiency was 90.3%
when the input and output voltages are 3.3 V and 1.8 V, respectively.
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