PSPICE SIMULATION SCHEMATIC DIAGRAM PFC UPS 2KVA ONLINE

 

SCHEMATIC PSPICE SIMULATION OF A HALF BRIDGE SINGLE PHASE DC-AC INVERTER USING PWM SWITCHING WITH NON LINEAR LOAD

 

ENERGIZEI CAST COM DOUTOR ELETRÔNICA DE POTÊNCIA (UFC)LUIS DANIEL BEZERRA PROFESSOR NO IFCE MARACANAU CEARÁ BRASIL

 

Analysis of Phase-Locked Loop Filter Delay on Transient Stability of Grid-Following Converters by Chenglin Zhang *,Junru Chen and Wenjia Si-The College of Electrical Engineering, Xinjiang University,

 Abstract 

To ensure precise phase estimation within the q-axis of the phase-locked loop (PLL), integrating a filter into the q-axis loop is essential to mitigate grid-voltage harmonics. Nevertheless, the intrinsic delay characteristics of this filter impede PLL synchronization during significant grid disturbances. This study begins by developing mathematical models for three types of filters—moving-average filter (MAF) for eliminating odd harmonic components, dq-frame cascaded delayed signal cancellation (dqCDSC) filter, and notch filter (NF). Following the reduction in filter orders, a third-order nonlinear large-signal model of the PLL, incorporating an additional q-axis internal filter, is formulated. Using phase plane analysis, this study investigates the transient synchronism of the grid-following converter (GFL) and explores the influence of delay time constants from the three PLL filters on its behavior while delineating the boundaries of their basins of attraction. Theoretical findings indicate that, relative to the traditional SRF-PLL, incorporating an internal filter into the PLL compromises the transient synchronous stability of GFL. Specifically, greater filter delay time constants exacerbate the GFL’s vulnerability to transient instability amid substantial grid disturbances. Hence, careful consideration is essential when using MAF-PLL and NF-PLL in situations demanding high synchronization stability. The theoretical analyses are validated using Matlab/Simulink to verify their accuracy.

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DQ Impedance Reshaping of Three Phase Power-Controlled Grid Connected Inverter for Low-Frequency Stability Improvement Under Weak Grid Condition Zhou, Weihua; Wang, Yanbo; E. Torres-Olguin, Raymundo; Chen, Zhe-Department of Energy Technology, Aalborg University, Aalborg, Denmark

 DQ Impedance Reshaping of Three-Phase Power-Controlled Grid-Connected Inverter for Low-Frequency Stability Improvement Under Weak Grid Condition Weihua Zhou∗ , Yanbo Wang∗ , Raymundo E. Torres-Olguin† and Zhe Chen∗ ∗Department of Energy Technology, Aalborg University, Aalborg, Denmark 

 Abstract—Phase-locked loop (PLL) is commonly used to synchronize the phase angle of the injected current of voltage source grid-connected inverters (GCIs) with that of the voltage at point of common coupling. However, the quadrature-axis component of the dq impedance model of the GCIs presents negative resistance characteristics in low-frequency range due to the usage of the PLL, which may lead to low-frequency instability phenomena if the GCIs work under weak grid condition. This paper presents a dq impedance reshaping method of powercontrolled GCIs to eliminate the negative effect of PLL on lowfrequency stability. The dq impedance models of the GCIs under current and power control modes are first established using complex vector and complex transfer function theory. On its basis, the negative effects of PLL on current control loop and power control loop are theoretically derived. A grid voltage feedforward loop is then designed in the control system of the powercontrolled GCIs, where the parameters of the feed-forward loop are calculated. The effectiveness of the proposed dq impedance reshaping method is validated by frequency scanning results and time-domain simulation results.

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https://vbn.aau.dk/ws/portalfiles/portal/334511002/Manuscript_accepted_version.pdf