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sexta-feira, 27 de dezembro de 2024

An Improved Carrier-Based Discontinuous PWM Method with Phase-Current THD Reduction for Vienna Rectifier 비엔나 정류기의 상전류 THD 저감을 위한 개선된 불연속 변조 기법 Minseong Kim ․ Juyeon Lee ․ June-Seok Lee-The Transactions of the Korean Institute of Electrical Engineers, vol. 73, no. 12, pp. 2255~2263, 2024


 An Improved Carrier-Based Discontinuous PWM Method with Phase-Current THD Reduction for Vienna Rectifier 

 비엔나 정류기의 상전류 THD 저감을 위한 개선된 불연속 변조 기법 
 Minseong Kim ․ Juyeon Lee ․ June-Seok Lee 

 Abstract 
This paper proposes an improved CB-DPWM(Carrier-Based Discontinuous Pulse Width Modulation) method for the Vienna rectifier. The conventional CB-DPWM methods clamp the reference voltage to zero during intervals where the Vienna rectifier's normal operating condition is not met due to the offset voltage for DPWM operation. However, these additional clamping intervals cause an increase in the phase current THD(Total Harmonic Distortion). In this paper, an improved CB-DPWM method is proposed to reduce the phase current THD of the Vienna rectifier by minimizing intervals where the reference voltage is zero. Furthermore, neutral point voltage control can be applied in the non-clamping regions to mitigate fluctuations in the neutral point voltage. Consequently, the proposed method can enhance the phase current THD while maintaining the advantage of reducing switching losses. The effectiveness of the proposed method is verified through simulations and experimental results.

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Design of Single-Phase PLL with DC Offset Rejection DC 오프셋 제거 성능을 갖는 단상 PLL 설계 Chan-Gi Lee ․ Kwang-Woon Lee ․ Sang-Il Kim-The Transactions of the Korean Institute of Electrical Engineers, vol. 73, no. 12, pp. 2231~2238, 2024


 Design of Single-Phase PLL with DC Offset Rejection DC
오프셋 제거 성능을 갖는 단상 PLL 설계 Chan-Gi Lee ․ Kwang-Woon Lee ․ Sang-Il Kim 이찬기* ․ 이광운** ․ 김상일 

 Abstract 
To control grid-connected inverters, grid synchronization is essential, and a Phase-Locked Loop (PLL) technique is commonly applied for this purpose. Among various PLL techniques, the Second Order Generalized Integrator (SOGI)-PLL is widely used due to its robustness against external noise. However, when the grid voltage contains a DC offset, the SOGI-PLL exhibits steady-state error, which is a limitation. To address this issue, this paper applies the Cascade SOGI (CSOGI)-PLL, which has a robust characteristic against DC offsets. Applying the CSOGI-PLL requires designing the parameters of a fourth-order transfer function and tracking the grid frequency by adjusting the resonant frequency. In this paper, a simplified design method using a second-order system for the damping coefficient of the CSOGI with a complex transfer function is proposed. A separate PLL is employed to update the resonant frequency of the CSOGI in response to rapid frequency variations, and frequency limitation and anti-windup control are applied to ensure stability during transients. To validate the effectiveness of the proposed method, simulations and experiments were conducted.

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FOUR-LEVEL THREE-PHASE INVERTER WITH REDUCED COMPONENT COUNT FOR LOW AND MEDIUM VOLTAGE APPLICATIONS V Sree Lakshmi, PG Scholar, Dept of EEE, JNTUA CEA, Ananthapuramu, Andhra Pradesh, India. : J Suresh, Research Scholar, Dept of EEE, JNTUA CEA, Ananthapuramu, Andhra Pradesh, India. : Dr R Kiranmayi, Professor, Dept of EEE, JNTUA CEA, Ananthapuramu, Andhra Pradesh, India. :


 FOUR-LEVEL THREE-PHASE INVERTER WITH REDUCED COMPONENT COUNT FOR LOW AND MEDIUM VOLTAGE APPLICATIONS

 V Sree Lakshmi, PG Scholar, Dept of EEE, JNTUA CEA, Ananthapuramu,Andhra Pradesh, India. 
 J Suresh, Research Scholar, Dept of EEE, JNTUA CEA, Ananthapuramu, Andhra Pradesh, India. :
 Dr R Kiranmayi, Professor, Dept of EEE, JNTUA CEA, Ananthapuramu, Andhra Pradesh, India. 

 ABSTRACT 
This paper proposes a novel three-phase topology with a reduced component count for low and medium-voltage systems. It requires three bidirectional switches and twelve unidirectional switches for producing four-level voltages without using flying capacitors or clamping diodes, reducing the size, cost, and losses. Removing flying capacitors and clamping diodes allows it to simplify control algorithms and increase the reliability, efficiency, and lifetime. A modified low-frequency modulation (LFM) scheme is developed and implemented on the proposed topology to produce a staircase voltage with four steps. Further, a level-shifted pulse width modulation (LSPWM) is used to reduce the filter size and increase the output voltage controllability. In this study, a voltage balancing control algorithm is executed to balance the DC-link capacitor voltages. The performance of the proposed topology is numerically demonstrated and experimentally validated on an in-house test setup. Within the framework, the power loss distribution in switches and conversion efficiency of the proposed circuit are studied, and its main features are highlighted through a comparative study.

quinta-feira, 28 de novembro de 2024

100kW-Class SiC Inverter Design for Series Hybrid Electric Propulsion System of Military Vehicle-Seok-Hwan Moon ․ Sang-Soo Park ․ Sang-Yong Kim ․ Jin-Uk Kim ․ Jun-Ha Hwang ․ Jin-Su Gwon

This paper proposes the design process of an inverter for 100kW-class military vehicle applying SiC-MOSFET. The SIC-MOSFET was selected in consideration of the performance and ease of design of the SIC-MOSFET, and the gate driver, DC-link capacitor, and heat sink were designed in consideration of the fast switching characteristics of the SIC-MOSFET and EMI noise. The designed SIC-MOSFET inverter was verified performance of the switching device through Double Pulse Test experiments and the performance of the inverter was verified by dynamo experiments. The Transactions of the Korean Institute of Electrical Engineers, vol. 73, no. 11, pp. 1958~1966, 2024