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Design of Single-Phase PLL with DC Offset Rejection DC
오프셋 제거 성능을 갖는 단상 PLL 설계
Chan-Gi Lee ․ Kwang-Woon Lee ․ Sang-Il Kim
이찬기* ․ 이광운** ․ 김상일
Abstract
To control grid-connected inverters, grid synchronization is essential, and a Phase-Locked Loop (PLL) technique is commonly
applied for this purpose. Among various PLL techniques, the Second Order Generalized Integrator (SOGI)-PLL is widely used due
to its robustness against external noise. However, when the grid voltage contains a DC offset, the SOGI-PLL exhibits steady-state
error, which is a limitation. To address this issue, this paper applies the Cascade SOGI (CSOGI)-PLL, which has a robust
characteristic against DC offsets. Applying the CSOGI-PLL requires designing the parameters of a fourth-order transfer function and
tracking the grid frequency by adjusting the resonant frequency. In this paper, a simplified design method using a second-order
system for the damping coefficient of the CSOGI with a complex transfer function is proposed. A separate PLL is employed to
update the resonant frequency of the CSOGI in response to rapid frequency variations, and frequency limitation and anti-windup
control are applied to ensure stability during transients. To validate the effectiveness of the proposed method, simulations and
experiments were conducted.
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