AUTOR DO BLOG ENG.ARMANDO CAVERO MIRANDA SÃO PAULO BRASIL

"OBRIGADO DEUS PELA VIDA,PELA MINHA FAMILIA,PELO TRABALHO,PELO PÃO DE CADA DIA,PROTEGENOS DO MAL"

"OBRIGADO DEUS PELA VIDA,PELA MINHA FAMILIA,PELO TRABALHO,PELO PÃO DE CADA DIA,PROTEGENOS  DO MAL"
"OBRIGADO DEUS PELA VIDA,PELA MINHA FAMILIA,PELO TRABALHO,PELO PÃO DE CADA DIA,PROTEGENOS DO MAL"

“SE SEUS PROJETOS FOREM PARA UM ANO,SEMEIE O GRÂO.SE FOREM PARA DEZ ANOS,PLANTE UMA ÁRVORE.SE FOREM PARA CEM ANOS,EDUQUE O POVO.”

“Sixty years ago I knew everything; now I know nothing; education is a progressive discovery of our own ignorance. Will Durant”

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sábado, 28 de dezembro de 2024

Analysis and design of –PID controller for a quadrotor in the frequency domain- Alhassan Dodo Adamou Soudeize* , Ji-Sun Park* , Ho-Lim Choi*-j.inst.Korean.electr.electron.eng.Vol.28,No.3,253~260,September 2024


 Analysis and design of –PID controller for a quadrotor in the frequency domain Alhassan Dodo Adamou Soudeize*, Ji-Sun Park*, Ho-Lim Choi*

 Abstract 
In this paper, we propose an -PID controller for the altitude control of the quadrotor from the ground by considering the mass of the AR Drone and external disturbance. The first part consists of modeling the quadrotor and carrying out the system analysis with the proposed controller and the second part consists of carrying out the experiment in the lab to show that our control method along with the analysis coincides with the experiment.
 

sexta-feira, 27 de dezembro de 2024

Quadcopter stabilization by using PID controllers- Luis E. Romero, David F. Pozo, Jorge A. Rosales Universidad de Las Américas, Escuela Politécnica Nacional


 Quadcopter stabilization by using PID controllers Luis E. Romero1, David F. Pozo2, Jorge A. Rosales3 1 Escuela Politécnica Nacional, Ladrón de Guevara E11 - 253, Quito, Ecuador, EC170127. 2 IEEE Member, Universidad de Las Américas, Av. De los Granados E12-41 y Colimes esq., Quito, Ecuador, EC170125. 3 IEEE Member, Escuela Politécnica Nacional, Ladrón de Guevara E11 - 253, Quito, Ecuador, EC170127. Autores para correspondencia: luiseduromp@hotmail.com, david.pozo@udla.edu.ec, andres.rosales@epn.edu.ec Fecha de recepción: 21 de septiembre de 2014 - Fecha de aceptación: 17 de octubre de 2014 

 RESUMEN 
En este trabajo se presenta la estabilización de un cuadricóptero mediante el uso de controladores PID para la regulación de sus 4 movimientos básicos: ángulos de alabeo, cabeceo, guiñada y altitud. La estabilización del sistema se realiza a partir de un modelo simplificado que facilita la implementación de controladores en un sistema SISO, demostrando efectividad dentro de un rango de ±10° para los ángulos de alabeo y cabeceo y rango completo en guiñada y altitud. El módulo del controlador PID es diseñado para ser usado en cuadricópteros comerciales y ha sido implementado en base a sensores inerciales y ultrasónicos. Además, el sistema cuenta con una interface para observar el desempeño de la aeronave durante el vuelo.
 ABSTRACT
 This work presents the stabilization of a quadcopter by using PID controllers to regulate its four basic movements: roll, pitch, yaw angles, and altitude. The stabilization of the system is made from a simplified model which makes easier the implementation of controllers on a SISO system, showing effectiveness within a range of ±10° for a roll and pitch angles and a full range on yaw angle and altitude. The PID controller module is designed to be used with commercial quadcopters and it has been implemented using inertial and ultrasonic sensors. Furthermore, the system also features a wireless interface to observe the aircraft performance during the flight.

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An Improved Carrier-Based Discontinuous PWM Method with Phase-Current THD Reduction for Vienna Rectifier 비엔나 정류기의 상전류 THD 저감을 위한 개선된 불연속 변조 기법 Minseong Kim ․ Juyeon Lee ․ June-Seok Lee-The Transactions of the Korean Institute of Electrical Engineers, vol. 73, no. 12, pp. 2255~2263, 2024


 An Improved Carrier-Based Discontinuous PWM Method with Phase-Current THD Reduction for Vienna Rectifier 

 비엔나 정류기의 상전류 THD 저감을 위한 개선된 불연속 변조 기법 
 Minseong Kim ․ Juyeon Lee ․ June-Seok Lee 

 Abstract 
This paper proposes an improved CB-DPWM(Carrier-Based Discontinuous Pulse Width Modulation) method for the Vienna rectifier. The conventional CB-DPWM methods clamp the reference voltage to zero during intervals where the Vienna rectifier's normal operating condition is not met due to the offset voltage for DPWM operation. However, these additional clamping intervals cause an increase in the phase current THD(Total Harmonic Distortion). In this paper, an improved CB-DPWM method is proposed to reduce the phase current THD of the Vienna rectifier by minimizing intervals where the reference voltage is zero. Furthermore, neutral point voltage control can be applied in the non-clamping regions to mitigate fluctuations in the neutral point voltage. Consequently, the proposed method can enhance the phase current THD while maintaining the advantage of reducing switching losses. The effectiveness of the proposed method is verified through simulations and experimental results.

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Design of Single-Phase PLL with DC Offset Rejection DC 오프셋 제거 성능을 갖는 단상 PLL 설계 Chan-Gi Lee ․ Kwang-Woon Lee ․ Sang-Il Kim-The Transactions of the Korean Institute of Electrical Engineers, vol. 73, no. 12, pp. 2231~2238, 2024


 Design of Single-Phase PLL with DC Offset Rejection DC
오프셋 제거 성능을 갖는 단상 PLL 설계 Chan-Gi Lee ․ Kwang-Woon Lee ․ Sang-Il Kim 이찬기* ․ 이광운** ․ 김상일 

 Abstract 
To control grid-connected inverters, grid synchronization is essential, and a Phase-Locked Loop (PLL) technique is commonly applied for this purpose. Among various PLL techniques, the Second Order Generalized Integrator (SOGI)-PLL is widely used due to its robustness against external noise. However, when the grid voltage contains a DC offset, the SOGI-PLL exhibits steady-state error, which is a limitation. To address this issue, this paper applies the Cascade SOGI (CSOGI)-PLL, which has a robust characteristic against DC offsets. Applying the CSOGI-PLL requires designing the parameters of a fourth-order transfer function and tracking the grid frequency by adjusting the resonant frequency. In this paper, a simplified design method using a second-order system for the damping coefficient of the CSOGI with a complex transfer function is proposed. A separate PLL is employed to update the resonant frequency of the CSOGI in response to rapid frequency variations, and frequency limitation and anti-windup control are applied to ensure stability during transients. To validate the effectiveness of the proposed method, simulations and experiments were conducted.

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FOUR-LEVEL THREE-PHASE INVERTER WITH REDUCED COMPONENT COUNT FOR LOW AND MEDIUM VOLTAGE APPLICATIONS V Sree Lakshmi, PG Scholar, Dept of EEE, JNTUA CEA, Ananthapuramu, Andhra Pradesh, India. : J Suresh, Research Scholar, Dept of EEE, JNTUA CEA, Ananthapuramu, Andhra Pradesh, India. : Dr R Kiranmayi, Professor, Dept of EEE, JNTUA CEA, Ananthapuramu, Andhra Pradesh, India. :


 FOUR-LEVEL THREE-PHASE INVERTER WITH REDUCED COMPONENT COUNT FOR LOW AND MEDIUM VOLTAGE APPLICATIONS

 V Sree Lakshmi, PG Scholar, Dept of EEE, JNTUA CEA, Ananthapuramu,Andhra Pradesh, India. 
 J Suresh, Research Scholar, Dept of EEE, JNTUA CEA, Ananthapuramu, Andhra Pradesh, India. :
 Dr R Kiranmayi, Professor, Dept of EEE, JNTUA CEA, Ananthapuramu, Andhra Pradesh, India. 

 ABSTRACT 
This paper proposes a novel three-phase topology with a reduced component count for low and medium-voltage systems. It requires three bidirectional switches and twelve unidirectional switches for producing four-level voltages without using flying capacitors or clamping diodes, reducing the size, cost, and losses. Removing flying capacitors and clamping diodes allows it to simplify control algorithms and increase the reliability, efficiency, and lifetime. A modified low-frequency modulation (LFM) scheme is developed and implemented on the proposed topology to produce a staircase voltage with four steps. Further, a level-shifted pulse width modulation (LSPWM) is used to reduce the filter size and increase the output voltage controllability. In this study, a voltage balancing control algorithm is executed to balance the DC-link capacitor voltages. The performance of the proposed topology is numerically demonstrated and experimentally validated on an in-house test setup. Within the framework, the power loss distribution in switches and conversion efficiency of the proposed circuit are studied, and its main features are highlighted through a comparative study.