차 전지 보호회로의 저전력 설계 기법 = Low-power design technology of integrated circuits for rechargeable battery protection by Lee,Jong Hoon School of Electrical Engineering Kookmin University Seoul KOREA

Low-power design technology of integrated circuits for rechargeable battery protection by Lee,Jong Hoon- School of Electrical Engineering Kookmin University Seoul KOREA 

 ABSTRACT 

Lithium-ion secondary batteries feature small size, lightweight, and large capacity, which can be utilized in many portable products for a long period, such as cellular phones, camcorders, and notebook computers. But when the batteries become overcharged, the electrolyte solution is decomposed, gas is produced, the internal pressure increases, and metal lithium is precipitated, which can cause a risk of fire or explosion. If the battery is overdischarged, the electrolyte solution is decomposed causing the degradation of the battery performance. In order to prevent these problems, the use of a protection circuit is necessary. It monitors overcharging, overdischarging, and overcurrent states of the battery, and controls overall charging and discharging paths. In this dissertation, the low-power lithium-ion Battery-Protection Integrated Circuit (BPIC) for multi cell configuration is designed. The hardware sharing scheme with more precisely divided operating states in the detection range could reduce the power consumption significantly, especially during the normal state. In BPIC, the novel low-supply voltage low-power CMOS voltage reference circuit insensitive to temperature and supply voltage variations is designed. The circuit used the new temperature compensation technique and the proposed current-mode start-up circuit. Moreover the proposed voltage reference operates at sub-1V supply voltage and it is insensitive to the variation of P.V.T.(process, voltage and temperature). The TC(temperature coefficient) of 12.01 ppm/℃ over the range from -25℃ to 85℃ and the PSRR(power supply rejection rate) of 71.87-dB at 1.5V(±10%) supply voltage are simulated results of voltage reference. The proposed BPIC has been verified by HSPICE simulation and fabricated in a 0.35-um 2poly-4metal standard CMOS process.

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