Is SiC a Game Changer-CPES?-The Center for Power Electronics Systems-TUTORIAL CONGRESSO BRASILEIRO DE POTÊNCIA 2015-COBEP2015-SOUTHERN POWER ELECTRONIC CONFERENCE

 

Abstract

Over the last two decades there has been much exhilaration about the anticipated transformation of power electronics that SiC devices would bring, which has been accompanied by tremendous efforts by governments and companies around the developed world to meet those expectations. The successful commercial use of SiC Schottky diodes over the last ten years has helped improve efficiency and reduce size of power converters in several applications, but only in the last couple of years, several SiC active switching devices became commercially available at reasonable cost and volume. CPES has been involved all along in characterizing the newest SiC devices and evaluating their potential to change existing applications and open completely new ones.

CPES-The Center for Power Electronics Systems (CPES), with annual research expenditures of $6-7 million dollars, is dedicated to improving electrical power processing and distribution that impact systems of all sizes – from battery-operated electronics to vehicles to regional and national electrical distribution systems.

VIEW FULL TUTORIAL:http://www.cobepspec2015.ufc.br/wp-content/uploads/2015/12/t1.pdf

DEVELOPMENT OF 30KVA INVERTER USING SIC MOSFET FOR 180◦C AMBIENT TEMPERATURE OPERATION Feng Qi1, Miao Wang, Longya Xu, Bo Zhao, Zhe Zhou 1The Ohio State University, USA -Smart Grid Research Institute of SGCC, China

DEVELOPMENT OF 30KVA INVERTER USING SIC MOSFET

FOR 180◦C AMBIENT TEMPERATURE OPERATION

Feng Qi1, Miao Wang1, Longya Xu1, Bo Zhao2, Zhe Zhou2

1The Ohio State University, USA

2Smart Grid Research Institute of SGCC, China

COBEP 2015 : 2015 IEEE 13th Brazilian Power Electronics Conference and 1st Southern Power Electronics Conference (COBEP/SPEC)

Abstract

 A 30kVA SiC MOSFET inverter is developed for 180°C ambient temperature operation.The entire inverter system is designed for high temperature (HT) except the DSP control circuit in room temperature environment. Power structure is designed using SiC MOSFETs, HT capacitors and a liquid cooling plate. The gate drivers with protections and power structure are placed in HT environment of 180○C. The prototype inverter has been built and successfully tested in 180○C environment at 30kVA for accumulative 5 hours without any problems.

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https://www.mediafire.com/file/gpd9w5bf75g7815/DEVELOPMENT+OF+30KVA+INVERTER+USING+SIC+MOSFET550.pdf/file

LLC DC to DC 공진 컨버터의 고주파 변압기 최적화 설계에 관한 연구 A study on an optimal design of the high frequency transformer in LLC DC to DC resonant converter -Jong-Hae Kim

 LLC DC to DC 공진 컨버터의 고주파 변압기 최적화 설계에 관한 연구 A study on an optimal design of the high frequency transformer in LLC DC to DC resonant converter 김 종 해* 

★ Jong-Hae Kim* 

 Abstract 

This paper presents an optimal design of the slim type high frequency transformer used in the LLC DC to DC resonant converter for 65-inch UHD-TV with the rated power of 315W. This paper also performs an optimal design of the slim type high frequency through core loss analysis, AC winding loss analysis, and optimization design of the winding arrangement of the LLC resonant transformer. Particularly, the high-efficiency and slim type high frequency transformer based on the obtained results from theoretical analysis in this paper is constructed in the interleaved and vertical winding structures of its transformer to realize the winding method of automatic type and minimize AC winding loss. The primary and secondary windings of the slim type high frequency transformer the vertical winding structure proposed in this paper used the Litz-wire windings, PCB and copper plate windings, respectively. Finally, an optimal design of the slim type high frequency transformer proposed in this paper was carried out through the experimental results to confirm the validity of theoretical analysis based on the simulation results using Maxwel

j.inst.Korean.electr.electron.eng.Vol.27,No.4,587~600,December 2023 논문번호 23-04-31 https：//doi.org/10.7471/ikeee.2023.27.4.587l 2D and 3D tool.

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https://www.mediafire.com/file/8lztogjj0ey6kdh/A+study+on+an+optimal+design+of+the+high+frequency+transformer+in+LLC+DC+to+DC+resonant+converter.pdf/file

ORIGINAL SOURCE:https://ikeee.jams.or.kr/co/locale.kci?lang=en_US

단상 태양광 발전용 고효율 벅부스트 하프브리지 인버터 A High-efficiency Buck-boost Half-bridge Inverter for Single-phase Photovoltaic Generation-Hyung-Min Ryu

단상 태양광 발전용 고효율 벅부스트 하프브리지 인버터 A High-efficiency Buck-boost Half-bridge Inverter for Single-phase Photovoltaic Generation 류 형 민* ★ Hyung-Min Ryu*

 j.inst.Korean.electr.electron.eng.Vol.27,No.4,450~455,December 2023

 Abstract 

Among single-phase photovoltaic inverters that can avoid excessive leakage current caused by the large parasitic capacitance of photovoltaic panels, a boost converter followed by a half-bridge inverter is the simplest and has the smallest leakage current. However, due to the high DC-link voltage, the rated voltage of the switching devices is high and the switching loss is large. This paper proposes a new circuit topology which can operate as a buck-boost inverter by adding two bidirectional switches to the output side of the half-bridge inverter instead of removing the boost converter. By reducing two stages of power conversion through the high-voltage DC-link to one stage, power loss can be reduced without increasing costs and leakage current. The feasibility of the proposed circuit topology is verified by computer simulation and power loss calculation.

 VIEW FULL TEXT:https://www.mediafire.com/file/k51fa1gx4e6wuv6/A+High-efficiency+Buck-boost+Half-bridge+Inverter+for+Single-phase+Photovoltaic+Generation-Hyung-Min+Ryu.pdf/file

Analysis and design of –PID controller for a quadrotor in the frequency domain- Alhassan Dodo Adamou Soudeize* , Ji-Sun Park* , Ho-Lim Choi*-j.inst.Korean.electr.electron.eng.Vol.28,No.3,253~260,September 2024

 Analysis and design of –PID controller for a quadrotor in the frequency domain Alhassan Dodo Adamou Soudeize*, Ji-Sun Park*, Ho-Lim Choi*

 Abstract 

In this paper, we propose an -PID controller for the altitude control of the quadrotor from the ground by considering the mass of the AR Drone and external disturbance. The first part consists of modeling the quadrotor and carrying out the system analysis with the proposed controller and the second part consists of carrying out the experiment in the lab to show that our control method along with the analysis coincides with the experiment.

 

VIEW FULL PAPER: https://www.mediafire.com/file/79yizbm64eli4sz/Analysis+and+design+of+–PID+controller+for+a+quadrotor+in+the+frequency+domain.pdf/file

Quadcopter stabilization by using PID controllers- Luis E. Romero, David F. Pozo, Jorge A. Rosales Universidad de Las Américas, Escuela Politécnica Nacional

 Quadcopter stabilization by using PID controllers Luis E. Romero1, David F. Pozo2, Jorge A. Rosales3 1 Escuela Politécnica Nacional, Ladrón de Guevara E11 - 253, Quito, Ecuador, EC170127. 2 IEEE Member, Universidad de Las Américas, Av. De los Granados E12-41 y Colimes esq., Quito, Ecuador, EC170125. 3 IEEE Member, Escuela Politécnica Nacional, Ladrón de Guevara E11 - 253, Quito, Ecuador, EC170127. Autores para correspondencia: luiseduromp@hotmail.com, david.pozo@udla.edu.ec, andres.rosales@epn.edu.ec Fecha de recepción: 21 de septiembre de 2014 - Fecha de aceptación: 17 de octubre de 2014 

 RESUMEN 

En este trabajo se presenta la estabilización de un cuadricóptero mediante el uso de controladores PID para la regulación de sus 4 movimientos básicos: ángulos de alabeo, cabeceo, guiñada y altitud. La estabilización del sistema se realiza a partir de un modelo simplificado que facilita la implementación de controladores en un sistema SISO, demostrando efectividad dentro de un rango de ±10° para los ángulos de alabeo y cabeceo y rango completo en guiñada y altitud. El módulo del controlador PID es diseñado para ser usado en cuadricópteros comerciales y ha sido implementado en base a sensores inerciales y ultrasónicos. Además, el sistema cuenta con una interface para observar el desempeño de la aeronave durante el vuelo.

 ABSTRACT

 This work presents the stabilization of a quadcopter by using PID controllers to regulate its four basic movements: roll, pitch, yaw angles, and altitude. The stabilization of the system is made from a simplified model which makes easier the implementation of controllers on a SISO system, showing effectiveness within a range of ±10° for a roll and pitch angles and a full range on yaw angle and altitude. The PID controller module is designed to be used with commercial quadcopters and it has been implemented using inertial and ultrasonic sensors. Furthermore, the system also features a wireless interface to observe the aircraft performance during the flight.

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https://publicaciones.ucuenca.edu.ec/ojs/index.php/maskana/article/view/585/509

An Improved Carrier-Based Discontinuous PWM Method with Phase-Current THD Reduction for Vienna Rectifier 비엔나 정류기의 상전류 THD 저감을 위한 개선된 불연속 변조 기법 Minseong Kim ․ Juyeon Lee ․ June-Seok Lee-The Transactions of the Korean Institute of Electrical Engineers, vol. 73, no. 12, pp. 2255~2263, 2024

 An Improved Carrier-Based Discontinuous PWM Method with Phase-Current THD Reduction for Vienna Rectifier 

 비엔나 정류기의 상전류 THD 저감을 위한 개선된 불연속 변조 기법 

 Minseong Kim ․ Juyeon Lee ․ June-Seok Lee 

 Abstract 

This paper proposes an improved CB-DPWM(Carrier-Based Discontinuous Pulse Width Modulation) method for the Vienna rectifier. The conventional CB-DPWM methods clamp the reference voltage to zero during intervals where the Vienna rectifier's normal operating condition is not met due to the offset voltage for DPWM operation. However, these additional clamping intervals cause an increase in the phase current THD(Total Harmonic Distortion). In this paper, an improved CB-DPWM method is proposed to reduce the phase current THD of the Vienna rectifier by minimizing intervals where the reference voltage is zero. Furthermore, neutral point voltage control can be applied in the non-clamping regions to mitigate fluctuations in the neutral point voltage. Consequently, the proposed method can enhance the phase current THD while maintaining the advantage of reducing switching losses. The effectiveness of the proposed method is verified through simulations and experimental results.

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http://journal.auric.kr/AURIC_OPEN_temp/RDOC/kiee01/kieet_202412_015.pdf

Design of Single-Phase PLL with DC Offset Rejection DC 오프셋 제거 성능을 갖는 단상 PLL 설계 Chan-Gi Lee ․ Kwang-Woon Lee ․ Sang-Il Kim-The Transactions of the Korean Institute of Electrical Engineers, vol. 73, no. 12, pp. 2231~2238, 2024

 Design of Single-Phase PLL with DC Offset Rejection DC

오프셋 제거 성능을 갖는 단상 PLL 설계 Chan-Gi Lee ․ Kwang-Woon Lee ․ Sang-Il Kim 이찬기* ․ 이광운** ․ 김상일 

 Abstract 

To control grid-connected inverters, grid synchronization is essential, and a Phase-Locked Loop (PLL) technique is commonly applied for this purpose. Among various PLL techniques, the Second Order Generalized Integrator (SOGI)-PLL is widely used due to its robustness against external noise. However, when the grid voltage contains a DC offset, the SOGI-PLL exhibits steady-state error, which is a limitation. To address this issue, this paper applies the Cascade SOGI (CSOGI)-PLL, which has a robust characteristic against DC offsets. Applying the CSOGI-PLL requires designing the parameters of a fourth-order transfer function and tracking the grid frequency by adjusting the resonant frequency. In this paper, a simplified design method using a second-order system for the damping coefficient of the CSOGI with a complex transfer function is proposed. A separate PLL is employed to update the resonant frequency of the CSOGI in response to rapid frequency variations, and frequency limitation and anti-windup control are applied to ensure stability during transients. To validate the effectiveness of the proposed method, simulations and experiments were conducted.

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:http://journal.auric.kr/AURIC_OPEN_temp/RDOC/kiee01/kieet_202412_012.pdf

FOUR-LEVEL THREE-PHASE INVERTER WITH REDUCED COMPONENT COUNT FOR LOW AND MEDIUM VOLTAGE APPLICATIONS V Sree Lakshmi, PG Scholar, Dept of EEE, JNTUA CEA, Ananthapuramu, Andhra Pradesh, India. : J Suresh, Research Scholar, Dept of EEE, JNTUA CEA, Ananthapuramu, Andhra Pradesh, India. : Dr R Kiranmayi, Professor, Dept of EEE, JNTUA CEA, Ananthapuramu, Andhra Pradesh, India. :

 FOUR-LEVEL THREE-PHASE INVERTER WITH REDUCED COMPONENT COUNT FOR LOW AND MEDIUM VOLTAGE APPLICATIONS

 V Sree Lakshmi, PG Scholar, Dept of EEE, JNTUA CEA, Ananthapuramu,Andhra Pradesh, India. 

 J Suresh, Research Scholar, Dept of EEE, JNTUA CEA, Ananthapuramu, Andhra Pradesh, India. :

 Dr R Kiranmayi, Professor, Dept of EEE, JNTUA CEA, Ananthapuramu, Andhra Pradesh, India. 

 ABSTRACT 

This paper proposes a novel three-phase topology with a reduced component count for low and medium-voltage systems. It requires three bidirectional switches and twelve unidirectional switches for producing four-level voltages without using flying capacitors or clamping diodes, reducing the size, cost, and losses. Removing flying capacitors and clamping diodes allows it to simplify control algorithms and increase the reliability, efficiency, and lifetime. A modified low-frequency modulation (LFM) scheme is developed and implemented on the proposed topology to produce a staircase voltage with four steps. Further, a level-shifted pulse width modulation (LSPWM) is used to reduce the filter size and increase the output voltage controllability. In this study, a voltage balancing control algorithm is executed to balance the DC-link capacitor voltages. The performance of the proposed topology is numerically demonstrated and experimentally validated on an in-house test setup. Within the framework, the power loss distribution in switches and conversion efficiency of the proposed circuit are studied, and its main features are highlighted through a comparative study.

VIEW FULL TEXT: http://www.journal-iiie-india.com/1_dec_23/10.2_dec.pdf